Verification Lead, Mixed Signal Design/PCIe PHY @ Intel Corporation
Verification Lead, 5G NR Modem PHY @ Intel Corporation
B. Eng., Computer Engineering @
Experienced Semiconductor and Computer Hardware Engineer, with active Security Clearance (Level-II), comprising over 10 years of high-speed PCB and FPGA/ASIC design/verification integration experience. Management and technical lead experience. Over 14 years industrial experience. Proficient in all levels of IP and Hardware development, from general architectural requirements to RTL, verification, validation and productization. Demonstrated experience deploying novel methodologies
Experienced Semiconductor and Computer Hardware Engineer, with active Security Clearance (Level-II), comprising over 10 years of high-speed PCB and FPGA/ASIC design/verification integration experience. Management and technical lead experience. Over 14 years industrial experience. Proficient in all levels of IP and Hardware development, from general architectural requirements to RTL, verification, validation and productization. Demonstrated experience deploying novel methodologies and test automation that provide a competitive advantage for IP development. Experienced devising and leading hardware initiatives in telecomm (4G LTE, Wimax), RF systems, FPGAs and ASIC. Skilled at introducing new verification methodologies and advanced computer simulation tools that help build reliable, defect-free hardware prior to production release.
Specialties: High-speed RTL/PCB design since 2005, covering various aspects of chip and circuit design/layout. Proficient in ultra high-speed IO, high-speed DAC/ADCs, PLLs, clock distribution trees, power, synthesizers, advanced ASIC verification (ABV, architecture, OOP, methodology, coverage, sims, regressions, OVM/UVM, SystemVerilog, C++, API/DPI), FPGA/DSP, DFT, PRBS, AXI4, NoC, IQ modulation, baseband, RF, PV, test equip. automation. biopharma, FDA/GLP, robotics, telecom, automotive, security clearance, CPU, memory sub-systems, SoC, Big Data, computer architecture.
Senior Design Architect & Verification Lead, Big Data @ Help create novel SoC systems that target Big Data applications. From August 2014 to Present (1 year 5 months) Senior ASIC Design/Layout Engineer, APU @ Microprocessor & Subsystem DV Lead (IP Deployed in APU/SOCs)
AXI4 Network-on-chip (NoC) DV Lead (IP Deployed in APU/SOCs)
North-Bridge/Graphics Voltage-Domain Crossing Verification (Microsoft Xbox One)
Novel Verification Methodology Prime for Clock-Crossing Verification
UVM Methodology Deployment and Consulting
PCIe PHY Integration Prime
PRBS Verification Improvement Methodology for APU/SOC PCIe Gen 1/2/3 From September 2010 to August 2014 (4 years) Toronto, Canada AreaSystems Engineering, Wireless @ DSP FPGA Design and Verification. Automated RF test stand development and verification of next generation wireless receiver system designs. From August 2010 to September 2010 (2 months) Ottawa, Canada AreaDSP FPGA Design, Wireless @ Design and Verification of Digital Signal Processing FPGAs involved in next generation electronic counter measures :
* Intellectual property (IP) and re-use methodology for RTL and verification (mixed-language, OVM, SystemVerilog, ABV).
* Comprehensive regression and automated build environments to support fpga release strategy on next generation platforms.
* Manage Linux FPGA tool flow.
* DSP, FIR design and IQ modulation techniques.
* Prime GPS-based and network synchronization FPGA design. From January 2009 to August 2010 (1 year 8 months) Ottawa, Canada AreaSilicon and Hardware Designer, 4G LTE/Wimax @ Responsible for delivering PCB and RTL design/verification for 4G Wireless BTS. WiMAX modem board and chip development. LTE Radio FPGA development :
* Hardware System Prime for Toshiba-Nortel Japanese WiMAX BTS joint venture. Propose WiMAX hardware re-use and prime General Specifications document for Japanese WiMAX Base-Station. Gained experience with Product Safety, Regulatory, and Reliability for markets outside NA.
* Digital Design Prime for IO controller chip on WiMAX Radio Distribution Unit (RDU). Architect and deliver RTL design into HW/SW integration testing. RDU supported up to 3 sectors.
* ASIC/FPGA Verification Sustaining : Maintain multi-chip (ASICs and FPGAs) system-level functional (RTL/gate-level) simulations for WiMAX.
* Initiated collaborative effort with leading Silicon sign-off CAD vendor for introducing advanced FPGA/ASIC verification methodology into Nortel 4G.
* LTE chip-level functional verification environments/testbenches.
* Hardware Design Owner of WiMAX Beta Modem. Responsible for the design and schematic capture of all WiMAX Beta Modem features. Release pcb design into ECO material drive on schedule. RoHS compliance.
* WiMAX modem daughter card prime. PCB floorplanning, high-speed differential and single-ended clock tree design, component selection.
* WiMAX hardware designer. Architect 3rd optical port and interface with Radio FPGA. From June 2006 to January 2009 (2 years 8 months) Ottawa, Canada AreaHardware Engineer (Contract), Optical @ Participate in the design of and help deliver into factory introduction 10G DWDM OC-192 Optical Line Card upgrades for Optera DX and HDX products:
• Participate in developing new high-speed (over 1 Gbps) SONET FRAMER FPGAs (Design Specifications, algorithm, pinout, algorithm development, PCB decoupling, device testing) to replace discontinued ASICs on both Optera DX Optical Line Regenerators and Optera Connect HDX. FPGAs carried both Ingress and Egress traffic, providing a centralized high-speed interface for both Client and Line traffic. Help with algorithm development of high-speed data channel synchronizers. PLLs and bulk/decoupling strategy.
• PCB and FPGA Testing. Liaison with manufacturing for factory introduction. From October 2005 to June 2006 (9 months) Ottawa, Canada AreaPrincipal Instrumentation Scientist, Pharmaceutical @ Identify and propose to management a robotic automation system for bio-assay based detection of pharmaceuticals in human clinical trials. Identify system and test requirements. Project management of a bid process. Collaborate with external hardware/software engineers on customized robotic applications. From June 1999 to August 2001 (2 years 3 months) Montreal, Canada AreaManager, Automotive Coatings @ Responsible for supervising 27 unionized autoworkers in the van plant paint shop. Responsible for daily production of panel assembly, prep work and spray booth one in the paint shop. Responsible for daily resource and task assignment. Rotating shift work. From 1989 to 1989 (less than a year)
B.Sc.Hons., Chemistry & Biology Medial @ Queen's University From 1989 to 1992 B. Eng., Computer Engineering @ Concordia University Kenneth Stevens is skilled in: ASIC, FPGA, SystemVerilog, SoC, RTL design, UVM, OVM, Functional Verification, Simulation, DV Leadership, Innovation, Collaborative Leadership, CMOS, OOP, DSP
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