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Joel Jamias

Senior Engineer

Sr. Principal Electrical Engineer | Digital ASIC and SoC Architect and Design Lead

Mission Viejo, California

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Joel Jamias's Email Addresses & Phone Numbers

Joel Jamias's Work Experience

Research In Motion

Senior Engineer

July 2010 to June 2011

Scotts Valley, CA


Senior Engineer

1998 to 2008

Santa Clara | Irvine | San Francisco | Sacramento | Folsom, CA


Principal Engineer

San Diego, CA

Joel Jamias's Education

Cornell University

BS, Electrical Engineering

Stanford University

graduate courses, Electrical Engineering

University of California, Los Angeles

MS, Electrical Engineering

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About Joel Jamias's Current Company

Research In Motion

ASIC Design -- Asset control core. H.264 AVC and H.265 HEVC video compression technologies for RIM BlackBerry smartphones. IEEE 1500 and IEEE 1149.1 interfaces.

Frequently Asked Questions about Joel Jamias

What company does Joel Jamias work for?

Joel Jamias works for Research In Motion

What is Joel Jamias's role at Research In Motion?

Joel Jamias is Senior Engineer

What is Joel Jamias's personal email address?

Joel Jamias's personal email address is d****[email protected]

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Joel Jamias's business email addresses are not available

What is Joel Jamias's Phone Number?

Joel Jamias's phone (213) ***-*916

What industry does Joel Jamias work in?

Joel Jamias works in the Semiconductors industry.

About Joel Jamias

đź“– Summary

Senior Engineer @ Research In Motion ASIC Design -- Asset control core. H.264 AVC and H.265 HEVC video compression technologies for RIM BlackBerry smartphones. IEEE 1500 and IEEE 1149.1 interfaces. From July 2010 to June 2011 (1 year) Scotts Valley, CASenior Engineer @ Intel ASIC & SoC Design -- memory controller hub with integrated graphics (Northbridge for mobile and desktop PC chipsets), 10 Gbps (OC192) SONET/SDH framer/mapper, i870 memory repeater hub for DDR channel (server/workstation chipset), and I/O controller hub in TSMC process (Southbridge for desktop PC chipset). DFT/DFx micro-architect and lead. Circuit design lead. Logic verification lead. Chaired a power reduction working group. Received three Intel IPED awards for technical contributions. From 1998 to 2008 (10 years) Santa Clara | Irvine | San Francisco | Sacramento | Folsom, CAPrincipal Engineer @ INNOPHASE Digital SoC design group lead. The group spans functional design (front end), verification, physical design (back end), DFT/DFD, and low power implementation. The group also works with systems engineering, test engineering, hardware-software integration, and mixed-signal verification. Technical project manager for the digital SoC design effort, with responsibilities that include planning, scheduling, resourcing, tracking, technical and logistical problem solving, streamlining, and risk mitigation. Championing a robust and schedule-driven Digital SoC Design Methodology for producing high-quality SoCs to bring to market. Also contributing through hands-on engineering work. (Hey, it's a startup company! What do you expect?) PRODUCTS—ultra-low power Smart Digital Radio SoCs for 5G and IoT applications. San Diego, CAEngineering Consultant -- Digital SoC Subsystems Architect and Design Lead @ Intel Corporation DFx (DFT, DFD, and DFM) micro-architect and design/integration lead for HPC subsystems in an AI accelerator SoC (10-nm process node). Architected the various DFX fabrics and chassis components for 6+ subsystems in the SoC. As the front-end DFX lead on subsystems, completed integration work while mentoring, training, and supervising others. Used my broad expertise to troubleshoot and debug faulty subsystems from other designers, resulting in high-quality subsystems and an intact reputation with customers. Also interfaced with management, as well as with verification, physical implementation, and physical design teams to resolve issues and opens both proactively and in a timely manner. Great teamwork across multiple disciplines and multiple sites led to successful completion of milestones despite limited resources. Influenced management on project direction and staffing. Started to get engaged in low power strategies and implementation. Worked initially as HBM subsystem logic lead. From 2018 to 2020 (2 years) Hudson, MA | Santa Clara, CASr. Principal Electrical Engineer @ Raytheon Digital and mixed-signal ASIC and SoC design for Space and Airborne Systems.* Digital Implementation Lead on multimillion-gate ASICs implemented at GHz clock speeds in nanometer process technologies.* Technical mentor and subject matter expert on Digital ASIC Design.* Key technical contributor, with results that led to many follow-on projects for the department. * Introduced advanced ASIC design techniques to significantly improve performance, power, and area metrics, generating five new multimillion-dollar projects. * Proposed and implemented innovative ideas and solutions (including onboard reliability with logic BIST), which were key technology differentiators that the customers coveted.* Used my broad expertise in digital ASIC design and allied fields to troubleshoot and debug faulty ASICs from other designers, resulting in high-quality follow-on ASICs and an intact reputation with customers.* Championed a robust design methodology for producing high-quality ASICs. * Raytheon coursework in radar systems and radar signal processing* Raytheon Six Sigma Specialist* Rstars Achievement Award -- May 2017* Recent papers and conference presentations: - "Extending Moore's Law ..." - Raytheon 2016 Information Systems and Computing (ISaC) Technology Network Symposium, Tucson, AZ (May 2016) - "Onboard Reliability and Fault Tolerance ..." - Raytheon 2017 Information Systems and Computing (ISaC) and Systems Engineering and Architecture (SE&A) Technology Networks Joint Symposium, Tewksbury, MA (April 2017) - "Reconfigurable Computing ..." - white paper - Raytheon Space and Airborne Systems 2017 Summer Innovation Challenge (June 2017) - "Neuromorphic Computing ..." - white paper - 2018 Raytheon Innovation Challenge (November 2017) - "Reconfigurable Computing Systems on a Chip (SoCs) ..." - white paper - 2018 Raytheon Innovation Challenge (November 2017)PRODUCTS—mixed-signal RF transceiver SoCs, and AESA radar ASICs. From 2015 to 2018 (3 years) El Segundo, CAEngineering Consultant -- ASIC and SoC Design @ Qualcomm | Irvine Sensors | PMC-Sierra | AMD | Teradyne | Boeing Boeing -- Huntington Beach, CADigital ASIC and SoC design for Defense, Space & Security.Teradyne -- Tualatin, ORHigh-Speed Digital ASIC Design for a test system.Qualcomm -- San Diego, CASoC Design -- multimedia subsystems for Snapdragon mobile station modem SoCs with integrated graphics (28-nm and 20-nm process technologies).AMD -- Boxborough, MAHigh-Speed Digital and Mixed-Signal ASIC Design -- IP blocks (RTL to GDS II in 28-nm process technology) for a high-speed DDR3 PHY interface.PMC-Sierra -- Burnaby, BC, CanadaASIC & SoC Design -- multi-service, multi-protocol optical transport network.Irvine Sensors -- Costa Mesa, CAASIC & FPGA Design -- cognitive image sensor based on convolutional neural networks. ASIC design lead.Qualcomm -- San Diego, CASoC Design -- DFT for Snapdragon mobile station modem SoCs with integrated graphics. From 2008 to 2015 (7 years) various locations -- my North American Tour on consulting gigsSenior Member of Technical Staff @ TRW Space & Electronics ASIC, FPGA, and Board (PCB) Design -- formatter multiplexer unit for spacecraft payloads, reconfigurable VXI command and low-speed data board for testing digital processor units and wideband analog units, and radiation hard 32-bit microprocessor ASIC chipset used in spacecraft payloads. Hardware design lead. Previously held a Secret Clearance. Received a TRW DPC award for technical contributions. From 1995 to 1998 (3 years) Redondo Beach, CASenior Associate Engineer @ IBM ASIC design lead -- ASIC design, verification, test, and integration. Board-level signal integrity. Custom VLSI macrocell design. PRODUCTS—SSA and ESCON data router for a RAID storage control unit subsystem, digital processors and controllers for high-end disk drive electronics, computerized PBX processor with storage, and predecessor to PowerPC. Completed IBM internal training courses in computer architecture, data communications, and telecommunications. Received two IBM SSD awards for technical contributions.SKILLS:Nanometer and very deep submicron ASIC/SoC design, encompassing micro-architecture, RTL/VHDL/Verilog logic design, synthesis, linting, CDC, behavioral and gate-level simulation verification and debug, formal verification, static timing analysis, floorplanning, timing-driven layout supervision, scan DFT/DFx and BIST, burn-in and fault test generation. Technical supervision. DSP, digital filter design, and image processing. MATLAB analysis. C programming. RTL to GDSII development of ASIC IP blocks. Analog and custom digital VLSI circuit design and layout. HSPICE and STARSIM circuit simulation. Silicon test and debug, hardware-software system integration, and supporting product test and manufacturing test. FPGA (Xilinx and Actel), PLD, and PCB design and debug. Signal integrity analysis and problem resolution. Scientific computing. Tcl/Perl scripting. EDA tools: Cadence (RC Physical/Genus, EDI/Innovus, Tempus, Voltus, Encounter Test/Modus, Encounter Conformal LEC formal verification, Incisive/Xcelium, Virtuoso, First Encounter), Mentor (ModelSim/QuestaSim, HyperLynx SI, Design Architect, DFT Advisor, FastScan ATPG, Calibre), Synopsys (Design Compiler, DC Ultra, IC Compiler/ICC, DFT Compiler, PrimeTime/PTSI, PTPX), LogicVision ET (Embedded Test 4.1). UNIX, Linux, and Windows operating systems. From 1987 to 1995 (8 years) Boca Raton, FL | San Jose, CA

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In a nutshell

Joel Jamias's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

4 year(s), 10 month(s)

Joel Jamias's Willingness to Change Jobs



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