2000 to 2001
Sr. ASIC design Engineer
2006 to 2008
Northrop Grumman Corporation
Member of Technical Staff Engineer
2001 to 2006
Sr. Staff ASIC Design Engineer
San Diego, California, United States
Staff ASIC design Engineer
November 2008 to July 2017
gate level custom VLSI circuit design: Static memory (BRAM), CLB, and DLL design. Gate level circuit design, DRC, LVS, functional verification, estimate the circuit area, floorplan and supervised customized layout. gate level custom VLSI circuit design: Static memory (BRAM), CLB, and DLL design. Gate level circuit design, DRC, LVS, functional verification, estimate the circuit area, floorplan and supervised customized layout.
What company does Jin Wu work for?
Jin Wu works for Xilinx
What is Jin Wu's role at Xilinx?
Jin Wu is VLSI design
What industry does Jin Wu work in?
Jin Wu works in the Semiconductors industry.
VLSI design @ Xilinx gate level custom VLSI circuit design: Static memory (BRAM), CLB, and DLL design. Gate level circuit design, DRC, LVS, functional verification, estimate the circuit area, floorplan and supervised customized layout. From 2000 to 2001 (1 year) Sr. ASIC design Engineer @ Qualcomm • Support In-house developed Memory Built-in Test insertion and verification on Qualcomm chips. Helped design teams to insert, verify and debug the MBIST. Worked on every Qualcomm chips.• Backdoor accessing design, implemented a module that interface with AHB, which allow user to access internet information via JTAG. Verification and documentation. Helped integration to the chip.• Involved in 45nm ROM design: rom cell modeling and simulation. Modeled and simulated different size of ROM, to ensure the design meets the spec. Fine-tuned the gate size to optimize the design. Wrote scripts to improve the design process. From 2006 to 2008 (2 years) Member of Technical Staff Engineer @ Northrop Grumman Corporation • Northrop Grumman, ASIC porting (under tight schedule): converted a FPGA design into an ASIC. The tasks are: IO buffer insertion, redesigned reset synchronization circuitry, scan-chain insertion, Boundary scan insertion, Static Timing Analysis, power estimation, SSO analysis, and functional test vectors generation. • Northrop Grumman, Phase Array Controller ASIC. Front-end designs and coding (VHDL), which included: design partitioning & architect, interface design, command and data handling, false-safe handling, and digital antenna controller. I also worked on formal verification, Static Timing Analysis, ASIC to FPGA conversion, Chip-level & Multi-Chip test benches, and test vector generation. • Northrop Grumman, F16 data link FPGA design: Giga-bit Ethernet TCP/IP, packet router, encryption/decryption engine• Northrop Grumman, Xilinx's embedded PowerPC project: used EDK tool and Chipscope tool to create a demo system.• Northrop Grumman, 1394 ASIC verifications: static timing analysis, simulations, and formal verification.• Northrop Grumman, Anti-Missile project: My task included: Architecture Trade off, DSP chip's TigerSHARC Interface handling, define communication protocol, command and data handling, and coding on 50% of the chip. From 2001 to 2006 (5 years) Sr. Staff ASIC Design Engineer @ Broadcom Limited • IP integration, control logic design for complex SOC ASICs. Owner of submodules of SOC. module level micro-architect design, documentation, RTL coding, spyglass (LINT, CDC), and synthesis. Built module level UVM bench and randomize tests. o Owner of RSA/ECC encryption/decryption acceleration module. Learned cryptographic. Design a module that reuse some IPs (RSA IP and DMA IP) that interfaces with AXI to offload software burden of encryption/decryption. Micro-architect my module, help to drive testplan and firmware.o Data movement between AXI and PCIe end point user I/F.. Own a small chip that has ARM, Flash memories, SRAM, AHB, ADC, DAC ect. San Diego, California, United StatesStaff ASIC design Engineer @ Marvell Semiconductor • Core member of a design team, and play an active role in our team. Well experienced in ASIC design flow, micro-architect my design, RTL coding, verification, chip level integration: IO pads & banks, analog modules, shielded analog signal routing; silicon brings up and ATE support for very high volume PHY products. • Rate Matching FIFO design and verification for 40G to 25G Ethernet PHY. Silicon came back with great success at first tape-out.• Ethernet Autoneg: Participated to automotive PHY (AutoPHY) IEEE 802.3bp development. Analysis, implement, and verify the proposed protocol that submitted to IEEE committee. Catch issues in some complex situations with proposed state machines and variables, provide suggest changes as well. Silicon had come back with great success (pass with first test-chip tapout).• Ethernet Precision Time Protocol (PTP) packet micro-processor design for 10G product: worked closely with architect for some trade off decision and implement 50% of RTL code. Verify the design in System Verilog.• MACSEC packet encryption/decryption IP integration From November 2008 to July 2017 (8 years 9 months)
Introversion (I), Intuition (N), Thinking (T), Judging (J)
4 year(s), 2 month(s)
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