Jeff Eichel's Email Addresses & Phone Numbers

Design Engineer @ Ungermann Bass/ UB Networks Developed hardware for state of the art networking systems. Responsible for all phases of development including writing specification, design, procurement of prototypes, debug and verification testing, creating documentation and doing anything necessary to produce high-value, highly reliable, low cost leading edge products. Gained thorough experience in networking design and concepts....

Design Engineer @ Ungermann Bass/ UB Networks Developed hardware for state of the art networking systems. Responsible for all phases of development including writing specification, design, procurement of prototypes, debug and verification testing, creating documentation and doing anything necessary to produce high-value, highly reliable, low cost leading edge products. Gained thorough experience in networking design and concepts. Used Verilog HDL, Synopsys, Neocad and other tools to design, verify and synthesize ASICs and FPGAs. From March 1989 to May 1996 (7 years 3 months) Adjunct Professor @ Pratt Institue and New York University Taught several undergraduate engineering and computer science classes. From February 1983 to June 1988 (5 years 5 months) Brooklyn and Greenwich Village, New York CityEngineer, Senior Engineer @ Harris Corp, Lockheed, ITT, Supreme Systems The early years of my career were spent at these four companies. Roles included development of factory and warehouse automation products, and military microcomputer, communications and ATE products. Worked with industrial programmable logic controllers, UARTS, Intel and Motorola microprocessors, IEEE 488. Mini and microcomputer interfaces, AMD 2900 bit-slice hardware and microprogramming, assembly and high level language programming. Programmable Logic Controllers. From August 1977 to September 1984 (7 years 2 months) Greater New York City AreaStaff Design Engineer @ Toshiba America Electronic Components, Inc. Started out as applications engineer helping customers develop ASICs to be mass produced by Toshiba. Position evolved into being a DFT specialist responsible for all test related functionality in customers ASICs. From May 1996 to June 2007 (11 years 2 months) Wakefield and Marlboro, MADFT/ATPG Contractor @ AMD Pre silicon verification for Styx/Seattle ARM-based high-density server microprocessor. Generation and verification of ATPG vectors using Mentor Tessent tools. (TestKompress and Fastscan). Coverage analysis and improvement. From August 2014 to December 2014 (5 months) Austin, Texas AreaConsultant @ Intel Corporation Post silicon verification. Verifying the DSI interface of Intel ATOM CPUs. This work includes maintenance and upgrades of FPGA based test board and helping engineers use that board in their testing. I used the Xilinx Virtex-6 family and Chipscope. Exposure to Simics. From October 2013 to January 2014 (4 months) Austin, Texas AreaSr. Electrical Engineer @ BAE Systems Southern NHSenior Electrical Engineer @ Raytheon FPGA design/development/debug. From April 2015 to March 2020 (5 years) TewksburyConsultant @ eInfochips Continued to work for Toshiba doing DFT tasks as a consultant through eInfochips.Current position is on site at Toshiba’s office in Marlboro MA. From June 2012 to March 2013 (10 months) Toshiba MarlboroSenior Staff Design Engineer @ Toshiba America Electronic Components All aspects of DFT. Scan. JTAG, and membist insertion. Vector generation and verification. Documentation. Communication with other groups, management, customers, off-shore consultants.Directly interfaced with customer on everything necessary for the development of state-of-the-art Toshiba ASICs to be used in their products. This position required training and knowledge of all of the state of the art EDA tools to design deep submicron ASICs, including design, synthesis, DFT insertion, simulation, verification, static timing analysis.Responsible for resolving all challenges that arise using such tools. Acquired many importantcontacts throughout industry. From June 2007 to July 2012 (5 years 2 months) Marlboro, MAAssistant Research Scientist @ New York University New York University. Designed and developed hardware for experimentalparallel computers. DRAM and cache memories, floating point coprocessors, AMD 29K RISC CPUdesign. PLDs, FPGAs and their tools. Supervisory experience. From September 1984 to January 1989 (4 years 5 months)