Javid Jaffari's Email Addresses & Phone Numbers

Co-Founder and CTO @ Spry Design Automation From 2008 to 2008 (less than a year) Waterloo, CanadaCompute Silicon Architect @ Facebook » Architect and Silicon-DRI of an AR user interface IP» HW/SW Co-design architect, from Algo to uArch Greater Seattle AreaStaff Engineer (Low Power Implementation @ QCT) @ Qualcomm Hardware Engineer/Lead at Qualcomm CDMA Technologies (QCT)‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾» From...

Co-Founder and CTO @ Spry Design Automation From 2008 to 2008 (less than a year) Waterloo, CanadaCompute Silicon Architect @ Facebook » Architect and Silicon-DRI of an AR user interface IP» HW/SW Co-design architect, from Algo to uArch Greater Seattle AreaStaff Engineer (Low Power Implementation @ QCT) @ Qualcomm Hardware Engineer/Lead at Qualcomm CDMA Technologies (QCT)‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾» From spec to RTL, designed a new hard macro IP block that controls power gating events. Successfully taped-out and brought-up for the commercial Snapdragon product line, at 20nm.» PDN lead for Snapdragon 808. Led the power delivery network design of the chip, package, and board, by a matrix organization of 40+ contributors. Supervised cross team activities on LPDDR4 power-delivery-network design and I/O jitter sign-off for Snapdragon 810. From June 2012 to November 2014 (2 years 6 months) Greater San Diego AreaMember Of Technical Staff @ Altera Software Engineering‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾» Developed (C++) power analysis engines for Altera’s FPGA devices in Quartus toolchain.» Maintained existing codes, built QoR, regression, unit, and integration tests. From January 2011 to June 2012 (1 year 6 months) Toronto, Canada AreaAlgorithm Researcher @ IGNIS Innovation Inc. Systems Engineering‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾» Developed novel machine learning and signal processing (PCA, Compressive Sensing, Markov Random Field) based algorithms for next-gen AMOLED display panels. From December 2009 to January 2011 (1 year 2 months) Waterloo, Canada AreaGraduate Research Intern @ Actel (now Microsemi) » Developed a new DSP power model and implemented in C++ for Actel’s FPGAs.» Automated DSP netlist generation for fixed point arithmetic macros. From June 2008 to November 2008 (6 months) Research Assistant @ University of Tehran » Implemented Electronic Design Automation tools in C++, for logic optimization and DFT.» Contributed to RTL design of a PCIe 1.0 core. From March 2003 to August 2005 (2 years 6 months) Principal Engineer, Product Architect @ Atlazo Inc Founding Member» Architect of an ultra-low power full chip SoC targeting healthcare wearable IoT market. » Architected and implemented an accelerator compute IP for energy efficient execution of signal processing and ML analytics-at-the-edge (NPE).» CPU and DSP vendor engagement.» Implementation and PPA analysis of audio/voice (keyword detection) and ML algorithms for a heterogeneous CPU/DSP/HWA compute architecture. From December 2016 to June 2018 (1 year 7 months) Greater San Diego AreaResearch Assistant @ University of Waterloo » Developed variance reduced Monte-Carlo methods and statistical optimization algorithms. Subsequently applied them to EDA solutions for IC yield analysis and improvement.» Implemented the researched on new EDA algorithms with 100K+ lines of C++ code.» 15+ publications in TCAD, ICCAD, DATE, DAC, ISQED, ISCAS. Received highly competitive OGS scholarship as an international student, and NSERC-PDF fellowship. From September 2005 to December 2009 (4 years 4 months) Waterloo, CanadaEngineering Manager @ Facebook » Leading the AR Silicon's Programmable Cores team for AR/VR CV IP: - CPU/DSP ISA Extensions and uArch design - CNN ML accelerators - HW/SW co-design - SW and algorithm mapping and optimization on customized DSPs Greater Seattle AreaStaff Engineer (SoC Architect @ Qualcomm Research) @ Qualcomm SoC Architect at Corporate R&D (Qualcomm Research)‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾» Designed an accelerator for ZLIB compression algorithm. Instrumented Android kernel, profiled the algorithm and mapped it from C to SystemC to Verilog, for PPA analysis.» Contributed in architecture and development of a Deep Convolutional Neural Network accelerator (NPU) for image recognition applications.» Proposed accelerating workloads in data centers: Apache Spark big data and Blockchain PoW.» Flexible and low-cost camera processor architecture (ISP). From November 2014 to December 2016 (2 years 2 months) Greater San Diego Area