BS, Computer Engineering @
University of Cincinnati
Experienced digital design engineer and technical team lead with an outstanding record of success in driving programs throughout all phases of their life cycle, including proposal development, requirement and specification definition, implementation, verification, and maintenance. Demonstrates a strong commitment to producing quality products through effective leadership and a meticulous attention to detail. Combines exemplary communication and technical
Experienced digital design engineer and technical team lead with an outstanding record of success in driving programs throughout all phases of their life cycle, including proposal development, requirement and specification definition, implementation, verification, and maintenance. Demonstrates a strong commitment to producing quality products through effective leadership and a meticulous attention to detail. Combines exemplary communication and technical skills with extensive experience developing and implementing wireless FPGA-based digital signal processing systems for Software Defined Radios (SDRs) and Intellectual Property (IP) cores to deliver products within time and budget constraints.
FPGA Developer @ • Designing high-performance systems to facilitate electronic trading
• Formerly GETCO LLC. (2012-2013) From July 2012 to Present (3 years 4 months) San Francisco Bay AreaSenior Digital Design Engineer @ • Continued development of the Wideband Networking Waveform (WNW) started at L-3 Nova Engineering.
• Planned the implementation of WNW’s multi-channel diversity mechanism to fit within the resource utilization requirements of the radio’s FPGA. From March 2012 to September 2012 (7 months) Cincinnati AreaSenior Digital Engineer @ • Led a multi-disciplinary team of seven engineers in implementing and validating a low resource utilization and low data rate transceiver from the ETSI DVB-S2 Specification, a European digital satellite-based television broadcasting standard. Performed proposal and bidding, assisted in planning and developing system architecture, led implementation team including developing VHDL and bit-true MATLAB models, and validated system using commercial tools to ensure compliance with the standard.
• Created and tested Mobile DDR interfacing and control components to assist in porting the Wideband Networking Waveform (WNW) to a new SDR platform by reducing RAM utilization within the FPGA.
• Performed a full CMMI SCAMPI appraisal suite that resulted in the company being officially rated by the Carnegie Mellon Software Engineering Institute (SEI) at Maturity Level 3.
• Led a team of four engineers through planning, implementation, and qualification testing of the SpeedNet Euro four channel 16PSK MANET Smart Grid radio capable of closing links of over four miles using a one watt power amplifier (PA). Performed proposal and bidding, planned and developed system architecture, led implementation team, and validated against system and Conformité Européenne (CE) mark requirements.
• Developed a WiMAX-compatible LDPC FEC Encoder core capable of achieving over 40 Mbps while maintaining requirements for low FPGA resource utilization across several different vendors and families.
• Worked directly with customers to develop and refine new business proposals based upon their needs while simultaneously reviewing prior similar projects to agree upon feasible schedule and budgetary milestones.
• Designed, implemented, and performed qualification testing for the All-Terrain Data Link (ATDL), a WNW OFDM-based radio capable of transmitting an HD video feed from an automated terrestrial reconnaissance vehicle at the US Army’s Aberdeen Proving Ground. From February 2008 to March 2012 (4 years 2 months) Cincinnati AreaComputer Engineering Co-op @ • Created MateCheck software tool as a cost-effective PC-based replacement for expensive proprietary turbine engine balancing machines by developing the hardware interfaces and software algorithms to pinpoint and resolve sources of imbalance within the engine rotor assemblies. Traveled to engine assembly facilities to teach assembly workers about the new balancing process and to assist with its implementation at the plants.
• Designed and implemented software to convert engine performance data into Air Force Technical Orders, reducing processing time from approximately six hours to only a few minutes per report. From September 2002 to April 2006 (3 years 8 months) Cincinnati Area
MS, Computer Engineering @ University of Cincinnati From 2005 to 2008 BS, Computer Engineering @ University of Cincinnati From 2000 to 2005 Jason Nemeth is skilled in: VHDL, MATLAB, C, Objective-C, C++, VLSI, VHDL-AMS, Java, FPGA, Xilinx, Altera, Windows, Linux, Mac OS X, iPhone Development, ModelSim, Quartus, Xcode, Logic Analyzer, Spectrum Analyzer, Oscilloscope, Software Defined Radio, Network Architecture, Network Design, Low Latency Trading, Low Latency, iOS development, Systems Engineering, Matlab, OS X, Digital Signal..., Algorithms, System Architecture, Verilog, Digital Signal..., Simulations, Embedded Systems
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