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Jagadish Rongali

Verification Consultant @ Microsoft

Jagadish Rongali Contact Details

San Francisco Bay Area
Verification Consultant @ Microsoft
Engineer III (Consultant) @ Qualcomm
Consultant @ Broadcom
B.Tech, Electrical and Electronics @ Jawaharlal Nehru Technological University

* Engineering professional with 8+ Years of Experience in ASIC/FPGA Design Verification, synthesis, timing analysis, formal verification, Pre and Post layout simulation for ASIC/FPGA Specialties: SoC verification using UVM, RTL Design using Verilog, Verification using System Verilog, C, C++, Perl Scripting for automation, FPGA Prototyping using Xilinx& Altera FPGAs. AMBA, CortexM0, CortexM3, CortexR5, CortexA9, Coresight, LCD, DDR, 

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