HARDWARE ENGINEER 2 at Microsoft
Irvine, California
HARDWARE ENGINEER 2 @ Microsoft Bellevue, WASummer Intern @ ITRI Ultra low voltage (ULV) design performance improvement under process variation From July 2013 to September 2013 (3 months) Hsingchu, TaiwanIC Engineer @ Beijing VoiceOn Co, Ltd. I designed an ASIC chip (VPU3010 V2) based on SMIC0.18um technology, and this chip has been successfully taped out in VoiceOn...
HARDWARE ENGINEER 2 @ Microsoft Bellevue, WASummer Intern @ ITRI Ultra low voltage (ULV) design performance improvement under process variation From July 2013 to September 2013 (3 months) Hsingchu, TaiwanIC Engineer @ Beijing VoiceOn Co, Ltd. I designed an ASIC chip (VPU3010 V2) based on SMIC0.18um technology, and this chip has been successfully taped out in VoiceOn Technology Co. Ltd., and the final test showed that the max frequency of this chip could achieve 160MHz. From March 2010 to July 2011 (1 year 5 months) Research Assistant and Cadence Teaching Assistant @ Missouri University of Science and Technology (formerly University of Missouri, Rolla) 2014.06-Now, High Power Radio-frequency Effects on PCB and Their Embedded Chip ElementsIn order to study the effects of high power radio-frequency on different circuits, an SRAM array, a PLL circuit, and a 8051 microprocessor are designed as test objects using 0.6um AMI library and will be taped-out in December of 2014. In this project, I am in charge of the microprocessor design which is written in Verilog. I have finished the pre-simulation stage and am working on verification based on Altera FPGA (DE II board). Meanwhile, I co-work with the SRAM circuit immunity mechanism, including the positive and negative EFTs to power supply and I/O pins, and RF injection to Power/ Ground panel. A simple 6T SRAM cell has been designed and tests are finished using cadence Spectre. The read/write delay changing are measured in order to observe the effects of EFTs on power panel. 2013.07-Now, Ultra-Low Voltage Design Performance Improvement under Process Variation Sub-threshold design provides a compelling approach for ultra-low voltage design. However, due to the exponential relationship between delay and threshold voltage, it is very sensitive to process variation and requires post-silicon tuning for delay compensation. In this project, the problem of post-silicon body biasing tuning for sub-threshold designs is firstly formulated as a linear constrained optimization model, and a novel adaptive filtering algorithm is further proposed to efficiently solve it. Experimental results on ISCAS85 designs using 65nm sub-threshold library suggest that our approach can improve the yield by up to 70% compared with a seemingly more intuitive approach. The algorithm has been implemented using C++ and Python. Research Assistant @ Tsinghua University 2007.01-2009.7, A speech recognition co-processor VPU3000 V2, was verified on Xilinx Virtex 5 FPGA and taped-out using 0.18 UMC technology. Furthermore, I implemented an ARM based SoC for speech recognition based on the Actel ProASIC series FPGA platform2007.01-2007.8, Full-custom Random Number Generator IC (0.6um tape out in Jun. 2007)This is the course project of IC Design and Practice, in which I finished the full-custom design and layout based on 0.6um technology. It was taped-out and successfully passed the test, and through this project, I became familiar with the full-custom IC design flow with icfb and Virtuoso, etc. From January 2007 to December 2009 (3 years) R&D Engineer IC Design 4 @ Broadcom Work for SoC integration team, Timing and Power AnalysisRTL designPower management controller design for SoCRS decoder in dsl rtl designSoC high speed bus RTL Design From July 2015 to June 2019 (4 years) Irvine, California
Microsoft
HARDWARE ENGINEER 2
Bellevue, WA
ITRI
Summer Intern
July 2013 to September 2013
Hsingchu, Taiwan
Beijing VoiceOn Co, Ltd.
IC Engineer
March 2010 to July 2011
Missouri University of Science and Technology (formerly University of Missouri, Rolla)
Research Assistant and Cadence Teaching Assistant
Tsinghua University
Research Assistant
January 2007 to December 2009
Broadcom
R&D Engineer IC Design 4
July 2015 to June 2019
Irvine, California
What company does Hui Geng work for?
Hui Geng works for Microsoft
What is Hui Geng's role at Microsoft?
Hui Geng is HARDWARE ENGINEER 2
What industry does Hui Geng work in?
Hui Geng works in the Electrical/Electronic Manufacturing industry.
Who are Hui Geng's colleagues?
Hui Geng's colleagues are Mimi Teoh, CHEE YONG, Yan Tandeta, Ahmed El-Gabaly, Dominic Lemire, Alister Zhao, Jeff Rollins, Sameer Goyal, Roman Pasternak, and Sudhir Sangappa
Enjoy unlimited access and discover candidates outside of LinkedIn
One billion email addresses and counting
Everything you need to engage with more prospects.
ContactOut is used by
76% of Fortune 500 companies
Hui Geng's Social Media Links
/company/m...