Specialties: Superscalar Processor Architecture, Low Power Design Techniques, Algorithm Design & Analysis, Data Structures, SysML, POSIX Threads, Multi-Threading Programming, Structured Parallel Programming, Computer Architecture, Cache Coherency Protocols, Operating Systems, Network Traffic Management Algorithms, QoS, Discrete Event Simulation, VLSI, VMM, SystemC, Architectural Modeling in System C/C++, System Verilog, System Verilog Assertions(SVA), C, C++/OOP, AOP, Perl, UNIX, TCL, IPv4/IPv6, Matlab, ASIC design verification, block design verification, Full Chip and Multi Chip Design Verification, Test Plan Development and Execution, Coverage Methodology, C++ STL, Python, SW for embedded multi-core systems, Interconnection Networks, Queueing Theory, Stochastic Modeling, L2/L3

Server Systems Performance Architect @ Currently working on architectural modeling of coherent interconnect and L2 subsystem for ARM processor based server systems. From July 2015 to Present (6 months) Raleigh-Durham, North Carolina AreaPerformance & Low Power SoC Architect @ Developed the following Ultra-low power solutions for next-gen mobile architectures: Hardware and software architecture for low-power infrastructure in Qualcomm's premium segment smartphone SoCs. Architecture Models to be used as a blue-print for hardware-based low-power design solutions for apps processor cluster, modem cores, GPU cores and sensor cores in smart phone SoCs. Architecture for dynamic clock voltage scaling for processor cores, NoCs and DDR in SoC. Architecture for hardware-based voltage regulator manager to control power consumption Architecture for Memory subsystem power-performance management Worked on use case based power performance optimization architectures. Worked on developing HW-SW solutions for removing SoC bottlenecks From July 2013 to July 2015 (2 years 1 month) Greater San Diego AreaSenior Hardware Engineer @ Worked on architectural modeling and design verification of Traffic manager/Scheduling engine blocks for next generation Edge router Network Processor Unit. Responsible for scheduler level debugging for functional, performance and QoS requirements. Worked on GRM (C++ model a.k.a Golden Reference Model)/RTL Co-simulation environment for Scheduler engine. Co-simulation infrastructure also helped us catch some key architectural issues in both domains and helped us catch single cycle and multi-cycle inconsistencies between GRM and RTL. Worked closely with designers on coverage addition for many bypass paths along the pipeline. Involved closely in RTL and coverage reviews. Test development to hit all coverage bins. Worked on Implementation Specification reviews of all blocks of scheduling engine Worked on Architecture Specification Document review of scheduling engine and this is used extensively by SW for configuring scheduling engine in the lab. From January 2013 to July 2013 (7 months) Hardware Engineer lll @ Worked on System level design verification (MultiChip DV) of ASICs on CRS-3 platform with main focus on end to end network traffic performance (throughput, latency & jitter) characterization under various configuration cases for different ASICs. Key emphasis was also laid on stressing the scheduler engine under various congestion/oversubscription and traffic mixture scenarios (audio, video, lp traffic) Worked on Full Chip Design Verification of next generation Edge & Core Router Network Processor Unit ASIC (functional and performance aspects). Worked on block design verification of global packet manager plus l3 processing engine for Core/Edge Router Network Processor Unit ASIC belonging to next generation of products. Worked on architectural modeling of ASICs in edge router(ASR series) and core router(CRS). Developed code for performance modeling as well for the ASICs. Special emphasis was laid on testing to see if latency & traffic rate budgets were met for certain class of traffic (High priority audio, High priority video, low priority traffic) under certain specified traffic and congestion(oversubscription) conditions Development of scoreboards, monitors, packet drivers, bandwidth checkers, processor request timeout checkers, l3 processing engine result checkers using System Verilog and VMM methodology Worked on testplan development and execution for all the above specified efforts. Worked on executing both directed/random functional feature testing, functional error testing, ECC/parity error testing as part of RTL design verification effort Worked on block dv completion checklist. Worked on post silicon verification (PSV) of scheduler and QoS ASIC in CRS-3. Developed automated infrastructure for performance and QoS testing of the ASIC also. The automated infrastructure relied on perl and made sure we had various configurations swept on the ASIC and implemented bandwidth and latency checkers giving result within certain specified configurable accuracy. From January 2008 to July 2013 (5 years 7 months) Hardware Engineer lll @ From 2008 to July 2013 (5 years) Hardware Intern @ Worked on architectural modeling of ASR series router egress line card using System C From April 2007 to September 2007 (6 months)

Master's, Electrical Engineering @ University of Michigan From 2006 to 2007 Bachelor's in Engineering, Electronics & Communication @ Visvesvaraya Technological University From 2001 to 2005 Harsh Patil is skilled in: ASIC, Debugging, SystemVerilog, TCL, Embedded Systems, Perl, C++, Functional Verification, Computer Architecture, Logic Design, Network Processors, RTL Design, SystemC, C, Verilog