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Frank Theo

Design Manager, Silicon Implementation Group @ MediaQ

Software Developer

San Francisco Bay Area

Ranked #793 out of 15,860 for Design Manager, Silicon Implementation Group in United States

Section title

Frank Theo's Email Addresses & Phone Numbers

Frank Theo's Work Experience

MediaQ

Design Manager, Silicon Implementation Group

2000 to 2002

Santa Clara, CA

SGI

Consultant

2000 to 2000

Moscape

Sr. Member of Technical Staff

1998 to 2000

Frank Theo's Education

The Ohio State University

MSEE, Electrical Engineering

University of Arizona

Bachelor's Degree, Electrical Engineering

Frank Theo's Professional Skills Radar Chart

Based on our findings, Frank Theo is ...

Leader
Methodical
Quiet

What's on Frank Theo's mind?

Based on our findings, Frank Theo is ...

56% Left Brained
44% Right Brained

Frank Theo's Estimated Salary Range

About Frank Theo's Current Company

MediaQ

Frequently Asked Questions about Frank Theo

What company does Frank Theo work for?

Frank Theo works for MediaQ


What is Frank Theo's role at MediaQ?

Frank Theo is Design Manager, Silicon Implementation Group


What is Frank Theo's personal email address?

Frank Theo's personal email address is f****[email protected]


What is Frank Theo's business email address?

Frank Theo's business email addresses are not available


What is Frank Theo's Phone Number?

Frank Theo's phone (**) *** *** 317


What industry does Frank Theo work in?

Frank Theo works in the Semiconductors industry.


About Frank Theo

📖 Summary

Design Manager, Silicon Implementation Group @ MediaQ From 2000 to 2002 (2 years) Santa Clara, CAConsultant @ SGI From 2000 to 2000 (less than a year) Sr. Member of Technical Staff @ Moscape From 1998 to 2000 (2 years) Senior Design Engineer, Microprocessor Group @ NEC Electronics From 1997 to 1998 (1 year) Santa Clara, CACircuit Design Engineer, Microprocessor Group @ Fujitsu Microelectronics From 1995 to 1997 (2 years) San Jose, CAStaff Design Engineer @ ARM Worked in memory compiler product development (45nm-130nm). Responsibilities: circuit design/fixes, margin analysis, characterization, layout supervision, EM/IR analysis, noise analysis, QA and product release. From 2006 to 2011 (5 years) Software Developer @ Asturia Technologies Architectured and implemented ECommerce market place platform from scratch. Web development using Ruby on Rails framework, Bootstrap, JQuery, CSS, HTML, and ReactJS.Implement RESTful APIs.Implement search features with ElasticSearch. Implement front-end apps using Angular 2Implement chat features using Action Cable/WebSocket and SMS messages using Twilio.Performed testing with RSpec, FactoryGirl, Capybara, and Selenium. Performed Continuous Integration with Jenkins. Run background jobs with Sidekiq.Perform code coverage and performance testing.Implement payment systems: paypal, and Stripe. Mountain ViewStaff Design Engineer @ SMI Worked in custom memory circuit design: Level 1 TLB (5 ports), 4/8-way set associative Instruction Cache Data and Tag Arrays in TSMC 28nm process. Responsibilities: circuit simulation, margin analysis, layout extraction, timing characterization, timing model generation, layout floor-planning,layout supervision, EM/IR analysis, noise analysis, and logical functional verification. From September 2011 to 2014 (3 years) Santa Clara, CAMember of Technical Staff @ Altera Worked in the development of Embedded Memory Block.Repsonsibilities: circuit optimization, pre and post-layout timing analysis, power analysis,signal integrity analysis, symbolic circuit verification, guided the place and route tasks for MACin 65nm TSMC process. From 2005 to 2006 (1 year) San Jose, CASenior Engineer (Band 9) @ IBM Worked in the development of Cell, XBOX, and Nintendo gaming processors.Responsibilities: performed circuit analysis, static timing analysis, and circuit modifications on L1 Tags, did circuit analysis and layout improvement on register files, did circuit design, layout, timing/power/noise analysis on CAMs, performed power and noise analysis on OTP ROM, worked on speed enhancement on L1 Cache, worked on verification on Effective-to-Real-Address Translator in 90 nm SOI technology, did a consulting on some memory modules for AMD. Performed evaluation on Innologic ESP-CV symbolic verification tool. From 2003 to 2005 (2 years) San Jose, CA


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In a nutshell

Frank Theo's Personality Type

Introversion (I), Intuition (N), Thinking (T), Judging (J)

Average Tenure

2 year(s), 1 month(s)

Frank Theo's Willingness to Change Jobs

Unlikely

Likely

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Frank Theo's Social Media Links

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