Douglas Kay
ASIC DFT, Technical Leader @ DSBU at Cisco
Engineering Consultant (DFT, DV, Big Data Analytic)
San Jose, California
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Douglas Kay's Email Addresses & Phone Numbers
Douglas Kay's Work Experience
DSBU at Cisco
ASIC DFT, Technical Leader
January 2013 to October 2014
3600 Cisco Way, SJC18/2
MFG at Cisco
ASIC Test, Technical Leader
July 2005 to December 2012
170 West Tasman Dr, SJC-M2, San Jose, CA 95134
Cisco
Technical Leader, ASIC DFT Engineer
December 1998 to June 2005
San Jose, CA
National Semiconductor
Engineering Project Manager
November 1996 to December 1998
Santa Clara, CA
Compass Design Automation at VLSI Technology
Principal Engineer
March 1993 to November 1996
San Jose, CA
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About Douglas Kay's Current Company
DSBU at CiscoASIC Design, Design for Test, Debug and Diagonosis. Post Silicom Validaiton. ASIC DFT Architect. Project Management, Six Sigma Plus Green Belt Certified. Desing IP development, ASIC Testing, Design Automation. JTAG, iJTAG, MBIST. LBIST, SCAN, Scan Dump. ASIC Design, Design for Test, Debug and Diagonosis. Post Silicom Validaiton. ASIC DFT Architect. Project Management, Six Sigma Plus Green Belt Certified. Desing IP development, ASIC Testing, Design Automation. JTAG, iJTAG, MBIST. LBIST, SCAN, Scan Dump.
Frequently Asked Questions about Douglas Kay
What company does Douglas Kay work for?
Douglas Kay works for DSBU at Cisco
What is Douglas Kay's role at DSBU at Cisco?
Douglas Kay is ASIC DFT, Technical Leader
What is Douglas Kay's personal email address?
Douglas Kay's personal email address is do****[email protected]
What is Douglas Kay's business email address?
Douglas Kay's business email address is d*****@cisco.com
What is Douglas Kay's Phone Number?
Douglas Kay's phone (213) ***-*210
What industry does Douglas Kay work in?
Douglas Kay works in the Semiconductors industry.
About Douglas Kay
📖 Summary
ASIC DFT, Technical Leader @ DSBU at Cisco ASIC Design, Design for Test, Debug and Diagonosis. Post Silicom Validaiton. ASIC DFT Architect. Project Management, Six Sigma Plus Green Belt Certified. Desing IP development, ASIC Testing, Design Automation. JTAG, iJTAG, MBIST. LBIST, SCAN, Scan Dump. From January 2013 to October 2014 (1 year 10 months) 3600 Cisco Way, SJC18/2ASIC Test, Technical Leader @ MFG at Cisco DFT, Diagnostics, Failure Analaysis of ASICs and Silicon Components, FPGA ptototyping, Silcon Device Testing, Characterization, and Monitoring From July 2005 to December 2012 (7 years 6 months) 170 West Tasman Dr, SJC-M2, San Jose, CA 95134Technical Leader, ASIC DFT Engineer @ Cisco o Developed DFT techniques, flows, and solutions handling various ASIC vendors, DFT tools, and different design methodologies by working with 10+ business unit design teams. o Implemented DFT features in ASICs using Scan, ATPG, MBIST, LBIST and JTAG on the selective design projects. From December 1998 to June 2005 (6 years 7 months) San Jose, CAEngineering Project Manager @ National Semiconductor o Managed the design Intellectual Property (IP) library (or Mega-Cell logic & memory blocks) development to enable design teams to share and use in their projects. o Imported the design blocks from previous designs, retargeted to the new process, packaged, and released them for the new designs. From November 1996 to December 1998 (2 years 2 months) Santa Clara, CAPrincipal Engineer @ Compass Design Automation at VLSI Technology o Led the development projects of various ASIC design libraries: standard cells, gate array, IO library, Custom libraries, SRAM compiler, and PLLo Developed the software and algorithms with respect to the design library development From March 1993 to November 1996 (3 years 9 months) San Jose, CA
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In a nutshell
Douglas Kay's Personality Type
Extraversion (E), Sensing (S), Thinking (T), Perceiving (P)
Average Tenure
4 year(s), 4 month(s)
Douglas Kay's Willingness to Change Jobs
Unlikely
Likely
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