• RTL development in Verilog including module level testing and full chip integration. • Leading Gate Level Simulation environment bring-up as well as debug expert. • Perl script writing for automating processes in pre-silicon verification environment and test creation. • Behavioral Functional Modules writing in VHDL/Verilog/System Verilog • Very tight work with teams abroad including often business trips. Cross site coordination among teams/disciplines in U.S.A and Israel. • Experience in C/C++ embedded programming for post-silicon system validation. • Experience with Verification tools: Questa/NCSIM/Verdi/Codelink/Certe • Technical leader and manager of all the students in the pre-silicon verification team. • SystemC – using for random tests generation for pre and post silicon verification. • System Verilog full chip test bench owner using: interfaces/classes/assertions/coverage models. • System Verilog AVM/OVM random testing for unit level and full chip level. • Presented at Synopsis SNUG 2008 - Advneced Low Power Verification Methodolgies. • Presented at Mentor Graphics EXPO 2008 -Advenced Verification Tools for debug HW and SW together. Specialties:Building up random verification environments for complex cellular chips. Expert in System Verilog AVM/OVM random testing. Using advanced tools like Certe Studio for System Verilog code development environment. Using Codelink debugger for SW tests debug within Questa Simulator, Debussy/Verdi/Siloti debug viewers experty

Verification technical lead @ From June 2014 to Present (1 year 5 months) Verification Leader @ From April 2013 to June 2014 (1 year 3 months) israelVerification Team Leader @ Senior Verification engineer From January 2010 to April 2013 (3 years 4 months) Sr. Verification Engineer @ From January 2007 to July 2009 (2 years 7 months) verification engineer @ From 2006 to 2007 (1 year) Verification Engineer and ASIC design @ During the period I was in charge of 2 products full chip verification. ASIC design - developing RTL modules for GSM modem. From August 2000 to August 2006 (6 years 1 month) Post and Pre Silicon Verification Eng. @ Have large expirience in post silicon system validation and acting as technical lead. In this period I ramped up post silicon random testing for system stress and promoted advanced validation methodologies. Developed embedded SW drivers for DMA, interrupts controllers and other peripherals. From August 2000 to August 2006 (6 years 1 month) verification engineer @ From 2006 to 2006 (less than a year) verification engineer @ From 2000 to 2006 (6 years)

Bachelor of Applied Science (B.A.Sc.) @ Netanya Academic College From 1998 to 2001 Claudio Yanqo is skilled in: SystemVerilog, Verilog, ASIC, RTL design, Debugging, SystemC, Hardware, Simulation, Functional Verification, Embedded Systems, VLSI, VHDL, SoC, Perl, C, RTL coding, C++, VCS, Hardware Verification, ModelSim, Unix, ARM, Assembly, AHB, Programming, Processors, Semiconductors, Testing, Digital Design, Logic Design, SPI, GSM, DFT, DSP, Java, EDA, Simulations, AMBA AHB, Embedded Software, Low-power Design, RTL Design