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Bharath Shashidhar

Electrical Engineer

Electrical Engineer at Pacific Microchip Corp.

Los Angeles, California

Section title

Bharath Shashidhar's Email Addresses & Phone Numbers

Bharath Shashidhar's Work Experience

Pacific Microchip Corp.

Electrical Engineer

January 2018 to February 2020

Culver City

Pacific Microchip Corp.

Design Engineer - Intern

October 2017 to December 2017

Culver City

UC Santa Barbara

Teaching Assistant

April 2016 to June 2016

Bharath Shashidhar's Education

The National Institute of Engineering, Mysore, India

Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

2010 to 2014

UC Santa Barbara

Master's degree, Computer Engineering

2015 to 2016

Bharath Shashidhar's Professional Skills Radar Chart

Based on our findings, Bharath Shashidhar is ...

Structured
Doer
Thoughtful

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Based on our findings, Bharath Shashidhar is ...

52% Left Brained
48% Right Brained

Bharath Shashidhar's Estimated Salary Range

About Bharath Shashidhar's Current Company

Pacific Microchip Corp.

 Designed test and validation setup to bring up 56G, 20G SAR ADCs and Spectrometero Characterized ADCs, PLL, JESD Tx Core, ESI Tx Core and calibration state machineso PCB Schematic Development, PSOC Firmware development and GUI design using C#o Working with 5GSps and 40GSps oscilloscopes, Spectrum analyzer and signal generator Implemented 8.75Gb/s per lane JESD204B interface with...

Frequently Asked Questions about Bharath Shashidhar

What company does Bharath Shashidhar work for?

Bharath Shashidhar works for Pacific Microchip Corp.


What is Bharath Shashidhar's role at Pacific Microchip Corp.?

Bharath Shashidhar is Electrical Engineer


What is Bharath Shashidhar's personal email address?

Bharath Shashidhar's personal email address is bh****[email protected]


What is Bharath Shashidhar's business email address?

Bharath Shashidhar's business email addresses are not available


What is Bharath Shashidhar's Phone Number?

Bharath Shashidhar's phone (213) ***-*378


What industry does Bharath Shashidhar work in?

Bharath Shashidhar works in the Semiconductors industry.


About Bharath Shashidhar

📖 Summary

Electrical Engineer @ Pacific Microchip Corp.  Designed test and validation setup to bring up 56G, 20G SAR ADCs and Spectrometero Characterized ADCs, PLL, JESD Tx Core, ESI Tx Core and calibration state machineso PCB Schematic Development, PSOC Firmware development and GUI design using C#o Working with 5GSps and 40GSps oscilloscopes, Spectrum analyzer and signal generator Implemented 8.75Gb/s per lane JESD204B interface with 64lanes (Virtex 7 Ultrascale)o Used Si5380 clock generator board for reference clocks, modified the on-chip registers to get the required custom frequency clock.o Developed matlab script for CDR and to decode 10b 8b for data captured through oscilloscope Implemented 10Gb/s per lane Efficient Serial Interface (ESI) with 14lanes (Virtex 7 Ultrascale)o Implemented vivado debug core (chipscope) to monitor critical control and data signals.o Developed Matlab script to decode a complex frame assembly from the ASIC Implemented a complex data accumulation system, Accumulated 320Mbps data from 12 ASICs into DDR2 Ram with iteration time of 10mso Virtex 5 on a custom PCB with 12 40Mb/s data input was captured and accumulated with a previous time sample data from DDr2.o Virtex 5 DDr2 multi burst interface with over 1Gb/s read and write data rate was achieved.o Implemented FT1248 (USB2 FTDI 232H) interface with data rate of 100Mbps Implemented 80MBps USB3 interface using Cypress Ez-Fx3 (50MHz) Cadence standard cell ASIC flow (sim: NCSim/Incisive/ Modelsim, synthesis: Genus, place/route: Innovus) targeting TSMC 28nm HPC  Familiar with RTL & gate-level simulation (GLS) flow, and System Verilog, UVM verification Flow From January 2018 to February 2020 (2 years 2 months) Culver CityDesign Engineer - Intern @ Pacific Microchip Corp. ➢ ASIC feasibility study for NASA○ Implementation of DSP and arithmetic RTL○ Implementation of UART communication between PC and FPGA○ Behavioral study using Matlab and Simulink○ Emulation on Virtex 5 and ISE○ Synthesis, Timing and Power analysis using Cadence Genus (Upgrade from RTL Compiler)○ Simulation using ModelSim From October 2017 to December 2017 (3 months) Culver CityTeaching Assistant @ UC Santa Barbara Teaching Assistant for ECE 2C - Circuits and DevicesThis course deals with RLC circuits and filters, Laplace transform, Sinusoidal analysis and diode circuits. From April 2016 to June 2016 (3 months) Teaching Assistant @ UC Santa Barbara Advance VLSI Design ECE 122BThis course includes Transmission line in IC, Timing analysis, Elmore delay, Cock tree synthesis, Different Logic Families(CDL,Pass Transistor,,,) Spice analysis transistor level. From December 2015 to March 2016 (4 months) ASIC Engineer @ Scalable Systems Research Labs Inc. ➢ Working on RTL implementation of u-architecture of a memory IP based on Hybrid Memory Cube. ➢ Implemented an ingress state machine that handles write and read requests to the Hybrid Memory Cube and Ternary Content Addressable memory. ➢ Writing Systemverilog testbench to verify the design, generating functional coverage reports. From March 2017 to September 2017 (7 months) Graduate Research Assistant @ UC Santa Barbara Implemented of SurfNoC RouterImplementation of a surf based Network on Chip router. Implemented a 148x20 bit buffer, Route computation unit capable of routing a 4x4 Taurus network. Round robin arbiter for allocating virtual channel and a crossbar. Clock and reset are implicit, the code is convertible to verilog and can be synthesized. Yosys was used to synthesize the hardware. From June 2015 to September 2015 (4 months) Research Assistant @ Power Research and Development Consultants Pvt Ltd Power Transmission, Distribution and Photo-Voltaic Systems From June 2011 to June 2013 (2 years 1 month)


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Introversion (I), Sensing (S), Thinking (T), Perceiving (P)

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0 year(s), 10 month(s)

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