Machine Learning and Data Science in Spintronics
San Francisco Bay Area
Member of Technical Staff, Technology Development
May 2015 to Present
Member of Technical Staff, Technology Research
June 2014 to April 2015
Principal Engineer, Technology Research
April 2013 to May 2014
Senior Engineer, Technology Research
August 2011 to March 2013
August 2010 to July 2011
• Enabled Write/Read margin simulations in memory array for various STT-MRAM applications • Developed SPICE based Monte-Carlo methods for magnetic tunneling junctions in MRAM • Performed data analysis and model validation for compact models • Analyzed magnetic shielding principles, methods and stray field immunity for MRAM die • Enabled Write/Read margin simulations in memory array for various STT-MRAM applications • Developed SPICE based Monte-Carlo methods for magnetic tunneling junctions in MRAM • Performed data analysis and model validation for compact models • Analyzed magnetic shielding principles, methods and stray field immunity for MRAM die
What company does Behtash Behin-Aein work for?
Behtash Behin-Aein works for GLOBALFOUNDRIES
What is Behtash Behin-Aein's role at GLOBALFOUNDRIES?
Behtash Behin-Aein is Member of Technical Staff, Technology Development
What industry does Behtash Behin-Aein work in?
Behtash Behin-Aein works in the Semiconductors industry.
Expert on physics and engineering of electronic devices with specialization on STT-MRAM memory devices and spin based computing for logic. - Author of 30+ technical publications and patents with 660+ citations - Speaker of 11 contributed and 8 invited talks - Lead author of a theory paper in the Nature Nanotechnology journal (Feb/2010) - Lead principal investigator for Department of Energy's ALCC award (2011) - Recipient of Proctor prize grant-in-aid of research from scientific research society Sigma XI featured in American Scientist (2012) - Co-author of a cover story paper in IEEE Transactions on Nanotechnology (March/2012) - Lead industry liaison for semiconductor research corporation on spin based devices (2012-2014) - Lead invited author for Materials Research Society’s bulletin (August/2014) - Distinguished industry associate for the Center for Spintronic Materials, Interfaces, and Novel Architectures (2014) - Center coordinator for C-SPIN at GLOBALFOUNDRIES - Supervisor for 5 interns pursuing PhD - Technical referee for: Nature Nanotechnology; IEEE Transactions on Nanotechnology; IEEE Electron Device Letters; IEEE Transactions on Electron Devices, International Magnetics Conference, Magnetism and Magnetic Materials conference - Invited symposium organizer and session chair for international magnetics conference (2012) - Judge for semiconductor research corporation's (SRC) TECHCON conferenceMember of Technical Staff, Technology Development @ • Enabled Write/Read margin simulations in memory array for various STT-MRAM applications • Developed SPICE based Monte-Carlo methods for magnetic tunneling junctions in MRAM • Performed data analysis and model validation for compact models • Analyzed magnetic shielding principles, methods and stray field immunity for MRAM die From May 2015 to Present (8 months) Member of Technical Staff, Technology Research @ • Created SPICE compact models from scratch in HSPICE and Spectre for STT-MRAM bit cell • Modeled bit error rates due to thermal fluctuations with physics based Fokker-Planck formalism • Modeled coupling fields and their scaling behavior in Magnetic Tunnel Junctions From June 2014 to April 2015 (11 months) Principal Engineer, Technology Research @ • Performed analysis of SiGe FinFET PMOS transistors using the ballistic top-of-the-barrier transport model along with simulated atomistic band structure data. This was the first of its kind in terms of industrial FinFET channel sizes • Modeled heterogeneous Si/SiGe FinFET devices with TCAD process and device tool Sentaurus From April 2013 to May 2014 (1 year 2 months) Senior Engineer, Technology Research @ • Performed atomistic device modeling for band structure of SiGe FinFET PMOS transistors • Created the first simulation infrastructure for usage of Oakridge National Laboratory’s super-computing clusters at GLOBALFOUNDRIES From August 2011 to March 2013 (1 year 8 months) Postdoctoral Fellow @ • Created the lumped circuit model of spintronic encompassing coupled spin transport and magneto dynamics for memory and logic devices with colleagues at Purdue • Developed the first framework of formulating energy-delay characteristics and scaling of spintronic logic devices based on interaction of spins and magnets • Designed device-intrinsic directionality schemes in All Spin Logic based on geometry, spin polarization, voltage clocking schemes and electric field drift From August 2010 to July 2011 (1 year) PhD, Electrical Engineering @ Purdue University From 2004 to 2010 Bachelor of Science, Electrical and Computer Engineering @ Purdue University From 2000 to 2004 Behtash Behin-Aein is skilled in: Semiconductors, Simulations, Nanotechnology, Matlab, Electrical Engineering, Device Characterization, Electronics, Spintronics, Magnetics, Memory, CMOS, Physics, Design of Experiments, Semiconductor Device, Photolithography
Introversion (I), Intuition (N), Thinking (T), Judging (J)
1 year(s), 1 month(s)
There's 89% chance that Behtash Behin-Aein is seeking for new opportunities
Issued by Sigma XI (The Scientific Research Society) http://www.sigmaxi.org/about/news/2011SpecialGIAR.shtml · January 2012
Issued by Center for Spintronic Materials, Interfaces and Architectures · September 2014
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