Software Engineer, Network Operating System @ Arista Networks
Software Engineer, Network Switch SDK @ Broadcom
ASIC Architect, Network Switch ASIC @ Broadcom
Education:
Bachelor of Science, Electrical Engineering @
Stanford University
About:
I started my career building networking chips. Then I became interested in building networking software. My future interests include software-defined networking and distributed systems.
Software Engineer, Network Operating System @ • Responsibilities: Develop features for the Arista EOS, a network operating system for data center switches. From December 2013 to Present (2 years 1 month) Software Engineer, Network
I started my career building networking chips. Then I became interested in building networking software. My future interests include software-defined networking and distributed systems.
Software Engineer, Network Operating System @ • Responsibilities: Develop features for the Arista EOS, a network operating system for data center switches. From December 2013 to Present (2 years 1 month) Software Engineer, Network Switching SDK @ • Responsibilities: Design, develop, test, and maintain the Broadcom Network Switching SDK. The SDK implements a set of APIs that abstracts various L2 and L3 switching features of the StrataXGS series of network switching ASICs.
• Highlights: Designed and implemented APIs for the following features of the StrataXGS Trident-II ASIC (BCM56850): IP multicast, network interface virtualization, port extender, resilient hashing, virtual port routing, and virtual port LAG. From February 2009 to November 2013 (4 years 10 months) ASIC Architect, Network Switching ASICs @ • Responsibilities: Define packet processing architecture for the Broadcom StrataXGS series of network switching ASICs. These ASICs are fixed-function L2 and L3 packet processing chips for routers and switches.
• Highlights: Defined VPLS packet processing architecture of the StrataXGS Triumph ASIC (BCM56620), which laid the foundation for virtualized L2 switching features of subsequent generations of StrataXGS ASICs. The StrataXGS series of ASICs has become the market leading merchant silicons of the networking industry. From February 2004 to January 2009 (5 years) ASIC Design Engineer, Network Processors @ • Responsibilities: Design, implement, verify, and bring-up network processors. Network processors are programmable packet processing chips for network switches.
• Highlights: Co-led micro-architecture definition, RTL coding, and verification of the traffic management block of the nP3700 network processor. From May 1999 to January 2004 (4 years 9 months)
Master of Science, Electrical Engineering @ Stanford University From 1998 to 1999 Bachelor of Science, Electrical Engineering @ Stanford University From 1994 to 1998 Andrew Li is skilled in: Network Protocols, Networking Software, Networking ASICs, C, C++, Python
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