I am developing SystemVerilog UVM design verification software and VIP for mixed-signal audio products. Past experience includes: Design automation tool/flow development for analog, digital and mixed-signal design-entry and simulation. Dashboard development for metric driven chip design project management. Develop verification requirements management system. Develop version-control and release management coupled with functional verification (regression) flow automation and continuous integration. Develop physical design tool flow. Develop physical verification tool flow (DRC, LVS, PEX). QA and deploy device models. Standard Cell library development and characterization. External foundry PDK deployment and maintenance. Develop, deploy and maintain Content Management Flows (wiki's, issue tracking etc.) I have worked with EDA tools from Cadence, Mentor Graphics, Synopsys and others. Programming experience includes extensive work in Skill, Perl, Python, Tcl, Ruby, C/C++, Java and System Verilog. Also experienced in web development using HTML/JavaScript/MySQL/PostgreSQL/Sqlite. I have worked with several open source projects during my development work, for example, Jenkins, Django, Trac and Drupal. I have worked with third-party version control products like Perforce, SVN and CVS for developing in-house flows. My choice of OS is Linux (Redhat, Centos and Ubuntu are the distros I have experience in). Shell programming in Bash and Csh are one of my strengths (I prefer Bash over Csh). Specialties: Design Verification, SystemVerilog/UVM, Continuous Integration, Design Data Configuration Management, Mixed-Signal Design Flow, Digital Design Verification Flows, Standard cells, Physical Verification, PDK development, Software architecture, Software development, Shell Programming.

Design Verification Engineer @ Develop SystemVerilog/UVM software and VIP for design verification. From July 2012 to Present (3 years 6 months) Austin, Texas AreaCAD Engineer @ Develop and maintain front end design entry and simulation flows, back end verifications flows. Evaluates and integrate new tools/methodologies. From April 2008 to June 2012 (4 years 3 months) Austin, Texas AreaCAD Engineer @ From June 2005 to March 2008 (2 years 10 months) Graduate Research Assistant @ I created Java libraries for building SWF tags and files. I was successful in implementing a rudimentary set of SWF functionality using the developed software and play some level of animation in Flash. From June 2004 to May 2005 (1 year) Math faculty @ Taught mathematics and logical reasoning to undergraduate students. From January 2003 to July 2003 (7 months)

MS, EE @ Mississippi State University From 2003 to 2005 BE, Electronics Engineering @ Rajiv Gandhi Prodyogiki Vishwavidyalaya From 1998 to 2002 Bachelor of Engineering (B.E.), Electronics Engineering @ Shri Vaishnav Inst of Tech and Science From 1998 to 2002 UT@Austinchrist church boys'christ church boys' Abhishek Bhaduri is skilled in: Physical Verification, Mixed Signal, Simulation, Automation, Characterization, IC, EDA, DRC, VHDL, Verilog, Cadence Virtuoso, Simulations, FPGA, CMOS, SoC, Semiconductors